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MB86391 12, november 2001 product specification rev. 1.1 mpeg2 1chip audio/video encoder MB86391 product specification revision 1.1 12, november 2001 copyright ? fujitsu limited all rights reserved
fujitsu limited proprietary and co nfidential MB86391 12, november 2001 product specification rev. 1.1 u information contained in this specification is subject to change without notice for i mprovement. u no part of this specification may be reproduced or transmitted in any form or by any means for any purpose without the express written permission of fujitsu ltd. u the furnishing of this specification does not give users any license to fujitsu's industrial property rights. u fujitsu is not liable for infringement of third party patent rights, industrial property rights, or other rights that might result from the use of contents provided in this specification. u use of product in any manner that compli es with the mpeg - 2 standard is expressly prohibited without a license under applicable patents in the mpeg - 2 patent portfolio, which license is available from mpeg la, l.l.c., 250 steele street, suite 300, denver, colorado, usa 80206
fujitsu limited proprietary and co nfidential MB86391 12, november 2001 product specification rev. 1.1 contents 1 overview ................................ ................................ ................................ ................................ ......... 1 1.1 product overview ................................ ................................ ................................ ...................... 1 1.2 system configuration ................................ ................................ ................................ ................. 2 1.3 specification overview ................................ ................................ ................................ ............... 3 1.3.1 major items ................................ ................................ ................................ ................... 3 1.3.2 function list ................................ ................................ ................................ ................. 3 1.3.3 package ................................ ................................ ................................ ....................... 4 1.4 block diagram ................................ ................................ ................................ .......................... 5 2 pin description ................................ ................................ ................................ ................................ . 6 2.1 i/o signals ................................ ................................ ................................ ............................... 6 2.2 pin arrangement ................................ ................................ ................................ ....................... 7 2.2.1 pin arrangement diagram ................................ ................................ ............................... 7 2.2.2 pin numbers ................................ ................................ ................................ ................. 8 2.3 p in functions ................................ ................................ ................................ ............................ 9 2.3.1 overall control ................................ ................................ ................................ .............. 9 2.3.2 host/sdram interface ................................ ................................ ................................ .. 10 2.3.3 serial interface ................................ ................................ ................................ ........... 11 1 2.3.4 sdram interface for video encoding ................................ ................................ ............ 12 2 2.3.5 video input interface ................................ ................................ ................................ ... 13 3 2.3.6 audio input interface ................................ ................................ ................................ ... 14 4 2.3.7 bit stream output port ................................ ................................ ................................ . 15 5 2.3.8 test signals ................................ ................................ ................................ ............... 16 6 3 functional description ................................ ................................ ................................ .................... 17 7 3.1 host/sdram inte rface ................................ ................................ ................................ ............ 17 7 3.1.1 access by external master ................................ ................................ ........................... 18 8 3.1.1.1 MB86391 internal resource accessing ................................ .............................. 18 8 3.1.1.2 sdram accessing ................................ ................................ ........................... 20 3.1.1.3 external resource accessing ................................ ................................ ........... 24 4 3.1.2 internal controller master accessing ................................ ................................ ............. 26 6 3.1.2.1 external resource accessing ................................ ................................ ........... 26 6 3.1.2.2 external boot rom read ................................ ................................ ................. 28 8 3.1.3 interruption ................................ ................................ ................................ ................ 29 9 3.1.3.1 internal controller interrupt input (irq9:8) ................................ .......................... 29 9 3.1.3.2 host interrupt output (xextirpt) ................................ ................................ .... 29 9 3.1.4 address map ................................ ................................ ................................ ............... 30 3.2 serial interface ................................ ................................ ................................ ....................... 31 1
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specificat ion rev. 1.1 3.2.1 serial interface receive operations ................................ ................................ .............. 31 1 3.2.2 serial interface send operations ................................ ................................ .................. 32 2 3.3 sdram interface for video encoding ................................ ................................ ........................ 33 3 3.4 video input interface ................................ ................................ ................................ ............... 34 4 3.4.1 input formats ................................ ................................ ................................ ............. 35 5 3.5 audio input interface ................................ ................................ ................................ ............... 36 6 3.5.1 master/slave mode ................................ ................................ ................................ ...... 37 3.5.2 input formats ................................ ................................ ................................ ............. 37 7 3.6 bit stream output port ................................ ................................ ................................ ............ 3 8 8 3.7 error notification function ................................ ................................ ................................ ....... 41 1 3.8 boot operations ................................ ................................ ................................ ..................... 42 2 3.8.1 downloading from the external rom ................................ ................................ ............. 43 3 3.8.2 serial download ................................ ................................ ................................ .......... 43 3.8.3 direct sdram downloading ................................ ................................ ......................... 43 3 4 electrical characteristics (provisional target specifications) ................................ ................................ 44 4 4.1 maximum ratings ................................ ................................ ................................ ................... 44 4 4.2 recommended operating co nditions ................................ ................................ ......................... 45 4.2.1 recommended operating conditions ................................ ................................ ............. 45 4.2.2 precautions when connecting the power ................................ ................................ ....... 45 4.3 dc characteristics ................................ ................................ ................................ .................. 46 4.4 ac characteristics ................................ ................................ ................................ ................... 47 4.4.1 overall control ................................ ................................ ................................ ............ 47 4.4.1.1 clock input ................................ ................................ ................................ ...... 47 4.4.1.2 reset input ................................ ................................ ................................ ..... 48 4.4.2 host/sdram interface ................................ ................................ ................................ . 49 4. 4.2.1 host interface ................................ ................................ ................................ .. 49 4.4.2.2 sdram interface signals ................................ ................................ ................. 52 4.4.3 serial interface ................................ ................................ ................................ ............ 54 4.4.4 sdram interface for video encoding ................................ ................................ ............. 56 4.4.5 video input interface ................................ ................................ ................................ .... 58 4.4.6 audio input interface ................................ ................................ ................................ .... 59 4.4.7 bit stream output port ................................ ................................ ................................ .. 63
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 1 1 overview 1.1 product overview the m b86391 (mpeg2 1chip audio/video encoder ) is an lsi that accomplishes all of video encoding, audio encoding, and video and audio encode stream data multiplexing with a single chip rather than several lsis as in the past. this lsi enables you to minimize th e size, cost and power consumption of mpeg2 application systems, such as digital video recorders. an easy control command interface is achieved by firmware dedicated to the internal controller.
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 2 1.2 system configuration fig. 1.2 shows an example system configuration using the MB86391 . fig. 1.2 : system configuration (example) ) MB86391 16mbit sdram ( 16bit) 64mbit sdram ( 32bit) or system controller xmbreq, xbreq xbgrnt xbusen, busdir, xbgrnt 16mbit sdram ( 16bit) 64mbit sdram ( 32bit) or sdram control bu s switch d31:0, adrs27 :26, 17:2 , control mpeg2 decoder bit stream output port video i/f audio i/f audio input video input d/a audio output video output serial interface video encoding sdram controller /tbc sdram record/ com mu nication i/o external boot rom
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 3 1.3 specification overview 1.3.1 major items table 1.3.1 : major items model MB86391 function mpeg2 1chip audio/video encoder operating frequency 54m hz (27mhz for some ) [ 27mhz input clock frequency, 54mhz clock generated by internal pll] technology 0.18 m m , al 4 layers supply voltage i/o 3.0 to 3.6v , internal 1.65 to 1.95v power consumption t.b.d operating temperature ta = - 20 to 85 c package 208 pin hqfp(fpt - 208p - m04) 1.3.2 function list table 1.3.2 : function list encoding compliant to iso/iec13818 - 2 (mpeg2 video )mp@ml and iso/iec11172 - 2 (mpeg1 video ) screen size when interlacing at 29.97hz compatible with size 32m 32n less than 720 480 (m, n : any integers ) when interlacing at 25hz : compatible with size 32m 32n less than 720 576 (m, n : any integer s ) video input interface d1 8bit parallel, yc multiplex 8bit parallel video encoder bit rate max. 15mbps encoding method iso/iec11172 - 3 (mpeg1 audio ) layer 1/2 - compliant sampling frequency 32khz , 44.1khz , 48khz channel count 2 ( mono, stereo, dual, joint stereo ) audio input interface lr multiplex serial audio encoder bit rate max. 448kbps encoding method iso /iec11172 - 1 ( mpeg1 system ) iso/iec13818 - 1 ( mpeg2 system ps/ts) [can also output to mono media in es and pes formats. ] stream output 8bit parallel multiplexer bit rate max. 20mbps ( cbr/vbr) overall controller internal 32bit risc processor sdram i/f for video encoding connects two 16mbit ( 1m 16bit s ) or one 64mbit ( 2m 32bit s ) external memory interfac e host /sdram i/f connects two 16mbit ( 1m 16bit s ) or one 64mbit (2m 32bit s ) serial interface one internal port for overall controller boot and command i/f time base corrector absorbs timing errors due to disarrayed input video images by temporarily buffering before reading video input data on an sdram connected to the host/ sdram i/f .
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 4 1.3.3 package
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 5 1.4 block diagram fig. 1.4 shows a block outline diag ram of this lsi and table 1.4 lists the functional overviews of major blocks. fig. 1.4 : MB86391 block diagram table 1.4 : overview of major block functions block name functional overview video enco der encodes video data input from the tbc controller to create video streams. audio encoder encodes audio data input from outside to create audio streams. multiplexer multiplexes video and audio streams generated by video and audio encoders to generate 8bit parallel stream data for output to outside. controller controls the entire MB86391 using dedicated firmware. tbc controller stores video data input from outside in an external sdram and then input it to the video encoder. the tbc ( time base corre ctor) function is accomplished by buffering video data in the sdram. host /sdram interface controller arbitrates sdram and MB86391 internal register access requests from MB86391 internal blocks and external master devices. also used as the command interf ace with the host. serial interface controller downloads dedicated firmware to the external sdram via this interface at the time of serial booting. also used as a command interface with the host. video pes converter converts the format of video streams the video encoder has generated and outputs to the multiplexer. dma controller controls dma transfer among MB86391 blocks and external sdrams. boot rom stores the boot program for the internal controller. video encoder audio encoder controller (32bit risc processor ) multiplexer tbc controller serial interface controller boot rom host /sdram interface controller sram (8k 8) MB86391 serial interface host /sdram interface video encoding sdram interface audio input interface video input interface bit stream output port pll clock input (27mhz) 27mhz 54mhz
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 6 2 pin description 2.1 i/o signals fig. 2.1 shows the i/o signals of this lsi. fig. 2.1 : i/o signal diagram MB86391 clksel mclki xreset bclk adrs27:26 d31:0 adrs17:2 xas xrdwr xcs0 xcs5:4 xbmreq xbre q xbgrnt busdir xready xerror irq9:8 xspwe xspcas xspras spcke spsdclk sdadrs11:0 sddata31:0 xsdcs sddqm xsdwe xsdcas xsdras sdclk sdcke vclk xvsync xhsync field xvalid dvideo7:0 asclk adata alrck aclk sclk sdatain sd ataout test signals video encoding sdram interfaces (51 in total ) video input interfaces (13 in total) audio input interfaces (4 in total) serial interfaces (3 in total) (3 in total ) overall control signals ( 4 in total ) pllthr host /sdram interface s (71 in total ) streq sten tspssync stdata7:0 bit stream output ports (12 in total ) power/gnd (47 in total ) xbusen total external pin count : 208 xextirpt 12 32 8 2 16 32 2 2 47 3 8 stclk
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 7 2.2 pin arrangement 2.2.1 pin arrangement diagram fig. 2.2.1 : pin arrangement diagram stclk vddi d26 d27 xcs0 xcs4 xcs5 bclk busdir xbusen d28 vss vdde d24 d25 xextirpt xerror xreset vdde vss xbgrnt xbreq xbmreq irq8 irq9 avdd mclki pllthr clksel xready xrdwr xas avss sdataout sdatain sclk vddi stdata0 vss vdde avss stdata3 stdata2 stdata1 stdata6 stdata5 stdata4 avdd vddi tspssync sten stdata7 49 50 51 52 45 46 47 48 41 42 43 44 37 38 39 40 33 34 35 36 29 30 31 32 25 26 27 28 21 22 23 24 17 18 19 20 13 14 15 16 9 10 11 12 5 6 7 8 1 2 3 4 vss 208 53 d29 vdde 207 54 d30 xtst 206 55 d31 d22 streq 205 56 d23 aclk 204 index 57 alrck 203 58 d21 testmode 202 59 d20 vpdx 201 60 d19 adata 200 61 vdde asclk 199 62 vss vdde 198 63 d18 vss 197 64 d17 sdadrs11 196 65 d16 sdadrs10 195 66 vddi sdadrs0 194 67 d8 sdadrs1 193 68 d9 sdadrs2 192 69 d10 sdadrs9 191 70 d11 vss 190 71 d12 vdde 189 72 d13 sdadrs8 188 73 d14 sdadrs7 187 74 d15 sdadrs6 186 75 d7 sdadrs5 185 76 d6 vdde sdadrs4 184 77 vss sdadrs3 183 hqfp208(fpt-208p-m04) 78 d4 vddi 182 79 d5 sdclk 181 MB86391 80 sdcke 180 81 d3 xsdcs 179 82 vddi xsdras 178 83 d2 xsdcas 177 84 d1 xsdwe 176 85 d0 sddqm 175 86 vdde vdde 174 87 vss vss 173 88 adrs27 sddata16 172 89 adrs26 sddata17 171 90 adrs17 sddata18 170 91 adrs16 sddata19 169 92 adrs15 sddata20 168 93 xspras sddata21 167 94 xspcas vddi 166 95 xspwe sddata22 165 96 vddi sddata23 164 97 spsdclk sddata31 163 98 spcke sddata30 162 99 vss sddata29 161 100 vdde sddata28 160 101 adrs5 sddata27 159 102 adrs6 vss 158 103 adrs7 vdde 157 104 adrs8 108 107 106 105 112 111 110 109 116 115 114 113 120 119 118 117 124 123 122 121 128 127 126 125 132 131 130 129 136 135 134 133 140 139 138 137 144 143 142 141 148 147 146 145 152 151 150 149 156 155 154 153 vddi adrs11 adrs10 adrs9 adrs3 adrs4 vss vdde adrs14 adrs13 adrs12 adrs2 dvideo1 dvideo0 vdde vss dvideo5 dvideo4 dvideo3 dvideo2 xvalid vddi dvideo7 dvideo6 vclk xhsync xvsync field sddata9 sddata8 vss vdde sddata13 sddata12 sddata11 sddata10 sddata15 sddata14 vdde vss sddata4 sddata5 sddata6 sddata7 sddata1 sddata2 vddi sddata3 sddata26 sddata25 sddata24 sddata0
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 8 2.2.2 pin numbers table 2.2.2 : pin number l ist pin no. i/o pin name pin no. i/o pin name pin no. i/o pin name pin no. i/o pin name 1 - vddi 53 i/o d29 105 i/o adrs9 157 - vdde 2 o tspssync 54 i/o d30 106 i/o adrs10 158 - vss 3 o sten 55 i/o d31 107 i/o adrs11 159 i/o sddata27 4 o stdata7 56 i/ o d23 108 - vddi 160 i/o sddata28 5 o stdata6 57 i/o d22 109 - vdde 161 i/o sddata29 6 o stdata5 58 i/o d21 110 - vss 162 i/o sddata30 7 o stdata4 59 i/o d20 111 i/o adrs4 163 i/o sddata31 8 - avdd 60 i/o d19 112 i/o adrs3 164 i/o sddata23 9 - avss 61 - vdde 113 i/o adrs2 165 i/o sddata22 10 o stdata3 62 - vss 114 i/o adrs12 166 - vddi 11 o stdata2 63 i/o d18 115 i/o adrs13 167 i/o sddata21 12 o stdata1 64 i/o d17 116 i/o adrs14 168 i/o sddata20 13 o stdata0 65 i/o d16 117 - vss 169 i/o sddata19 1 4 - vss 66 - vddi 118 - vdde 170 i/o sddata18 15 - vdde 67 i/o d8 119 i dvideo0 171 i/o sddata17 16 i stclk 68 i/o d9 120 i dvideo1 172 i/o sddata16 17 o sdataout 69 i/o d10 121 i dvideo2 173 - vss 18 i sdatain 70 i/o d11 122 i dvideo3 174 - vdde 19 i sclk 71 i/o d12 123 i dvideo4 175 o sddqm 20 - vddi 72 i/o d13 124 i dvideo5 176 o xsdwe 21 i/o xready 73 i/o d14 125 i dvideo6 177 o xsdcas 22 i/o xrdwr 74 i/o d15 126 i dvideo7 178 o xsdras 23 i/o xas 75 i/o d7 127 - vddi 179 o xsdcs 24 - avss 76 i /o d6 128 i xvalid 180 o sdcke 25 - avdd 77 - vss 129 i field 181 o sdclk 26 i mclki 78 - vdde 130 i xvsync 182 - vddi 27 i pllthr 79 i/o d5 131 i xhsync 183 o sdadrs3 28 i clksel 80 i/o d4 132 i vclk 184 o sdadrs4 29 i xbreq 81 i/o d3 133 - vdde 185 o sdadrs5 30 i xbmreq 82 - vddi 134 - vss 186 o sdadrs6 31 i irq8 83 i/o d2 135 i/o sddata8 187 o sdadrs7 32 i irq9 84 i/o d1 136 i/o sddata9 188 o sdadrs8 33 i xreset 85 i/o d0 137 i/o sddata10 189 - vdde 34 - vdde 86 - vdde 138 i/o sddata11 190 - vs s 35 - vss 87 - vss 139 i/o sddata12 191 o sdadrs9 36 o xbgrnt 88 i/o adrs27 140 i/o sddata13 192 o sdadrs2 37 o busdir 89 i/o adrs26 141 - vss 193 o sdadrs1 38 o xbusen 90 i/o adrs17 142 - vdde 194 o sdadrs0 39 o xextirpt 91 i/o adrs16 143 i/o sddata 14 195 o sdadrs10 40 o xerror 92 i/o adrs15 144 i/o sddata15 196 o sdadrs11 41 o xcs0 93 o xspras 145 i/o sddata7 197 - vss 42 o xcs4 94 o xspcas 146 i/o sddata6 198 - vdde 43 o xcs5 95 o xspwe 147 i/o sddata5 199 i asclk 44 o bclk 96 - vddi 148 i/o s ddata4 200 i adata 45 - vss 97 o spsdclk 149 i/o sddata3 201 i vpdx 46 - vdde 98 o spcke 150 - vddi 202 i testmode 47 i/o d24 99 - vss 151 i/o sddata2 203 i/o alrck 48 i/o d25 100 - vdde 152 i/o sddata1 204 i/o aclk 49 - vddi 101 i/o adrs5 153 i/o sdd ata0 205 i streq 50 i/o d26 102 i/o adrs6 154 i/o sddata24 206 i xtst 51 i/o d27 103 i/o adrs7 155 i/o sddata25 207 - vdde 52 i/o d28 104 i/o adrs8 156 i/o sddata26 208 - vss vdde : 3.3v power supply, vddi : 1.8v power supply, avdd : 1.8v power supply to pll vss , avss : ground
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 9 2.3 pin functions the pin functions of this lsi are shown below. 2.3.1 overall control table 2.3.1 : overall control pins pin no. pin symbol pin name bit i/o active pull up / down description 28 clksel internal clock s elect 1 i - - internal controller operating frequency selection input pin. when the screen size is d1, select 54mhz operations. ? h ? = 54mhz operations ? l ? = 27mhz operations 26 mclki main clock input 1 i - - operating clock (27mhz) input pin 33 xreset reset 1 i l - reset signal input pin 27 pllthr pll through 1 i - - internal pll control signal input pin (see figure on page 52)
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 10 2.3.2 host /sdram interface table 2.3.2 : host /sdram interface pins pin no. pin symbol pin name bit i/o active pull up/down pin function 44 bclk bus clock 1 o - - host /sdram interface bus clock (27mhz) output pin 88,89 adrs27:26 address 27:26 2 i/o - - address ( upper 2bit s ) i/o pins 90 to 92, 116 to 114, 107 to 101, 111 to 113 adrs17:2 address 17:2 16 i/o - - a ddress ( lower 16bit s ) i/o pins 55 to 50,48,47, 56 to 60, 63 to 65, 74 to 67,75,76, 79 to 81, 83 to 85 d31:0 data31:0 32 i/o - - 32bit data i/o pins 32,31 irq9:8 interrupt request 9:8 2 i l pullup interrupt request input pins. when not in use, connect t o either open or vdde . 23 xas address strobe 1 i/o l - address strobe i/o pin 22 xrdwr read/write 1 i/o - - read/write i/o pin: ? h ? = read ? l ? = write 41 xcs0 chip select 0 1 o l pullup chip select 0 output pin 43,42 xcs5:4 chip select 5:4 2 o l - chi p select 5:4 output pins 30 xbmreq burst mode request 1 i l pullup burst transfer request input pin 29 xbreq bus request 1 i l pullup bus privilege request input pin 36 xbgrnt bus grant 1 o l - bus grant output pin 38 xbusen bus buffer enable 1 o l - b us buffer enable output pin 37 busdir bus buffer direction 1 o - - bus buffer direction control output pin 21 xready ready 1 i/o l - ready i/o pin 39 xextirpt external interrupt 1 o l - external host interruption request pin 40 xerror error 1 o l - err or output pin 95 xspwe write enable 1 o l - write enable output pin to sdram connected to host/sdram interface 94 xspcas column address strobe 1 o l - column address strobe output pin to sdram connected to host/sdram interface 93 xspras row address stro be 1 o l - row address strobe output pin to sdram connected to host/sdram interface 98 spcke clock enable 1 o h - clock enable output pin to sdram connected to host/sdram interface 97 spsdclk sdram clock 1 o - - clock output pin to sdram connected to hos t/sdram interface
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 11 2.3.3 serial interface table 2.3.3 : serial interface pins pin no. pin symbol pin name bit i/o active pull up/down pin function 19 sclk serial clock 1 i - - serial i/f serial clock input pin. 18 sdatain serial data input 1 i - - serial i/f data input pin. 17 sdataout serial data output 1 o - - serial i/f data output pin.
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 12 2.3.4 sdram interface for video encoding table 2.3.4 : sdram interface pins for video encoding pin no. pin symbol pin name bit i/o active pull up/down pin function 196,195,191, 188 to 183, 192 to 194 sdadrs11:0 sdram address 12 o - - address output (12bit s ) pins to sdram connected to the video encoding sdram interface 163 to 159, 156 to 154, 164,165, 167 to 172, 144,143, 140 to 135, 145 to 149, 151 to 153 sddata31:0 sdram data 32 i/o - pullup data i/o (32bits) pins to sdram connected to the video encoding sdram interface 175 sddqm input mask /output enable 1 o h - data mask output pin to sdram connected to the video encoding sdram interf ace 176 xsdwe write enable 1 o l - write enable output pin to sdram connected to the video encoding sdram interface 177 xsdcas column address strobe 1 o l - column address strobe output pin to sdram connected to the video encoding sdram interface 178 xs dras row address strobe 1 o l - row address strobe output pin to sdram connected to the video encoding sdram interface 179 xsdcs chip select 1 o l - chip select output pin to sdram connected to the video encoding sdram interface 180 sdcke clock enable 1 o h - clock enable output pin to sdram connected to the video encoding sdram interface 181 sdclk sdram clock 1 o - - clock output pin to sdram connected to the video encoding sdram interface
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 13 2.3.5 video input interface table 2.3.5 : video i nput interface pins pin no. pin symbol pin name bit i/o active pull up/down pin function 132 vclk video clock 1 i - - video clock input pin. 130 xvsync vertical sync 1 i l - vertical sync input pin. 131 xhsync horizontal sync 1 i l - horizontal sync i nput pin. 129 field field 1 i - - field id input pin. 128 xvalid data valid 1 i l - input pin to indicate that valid data exists at dvideo7:0 . 126 to 119 dvideo7:0 digital video 8 i - - video input data input pin.
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 14 2.3.6 audio input interface table 2.3.6 : audio input interface pins pin no. pin symbol pin name bit i/o active pull up/down pin function 199 asclk audio system clock 1 i - - system clock input pin for audio. input clock 256 times the audio sampling frequency. must be in sync with mclki . 203 alrck audio l/r clock 1 i/o - - audio sampling clock pin. the pin outputs in master mode and inputs in slave mode . 204 aclk audio bit clock 1 i /o - - audio bit clock pin. the pin outputs in master mode and inputs in slave mode . 200 adat a audio serial data 1 i - - audio serial data input pin.
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 15 2.3.7 bit stream output port table 2.3.7 : bit stream output port pins pin no. pin symbol pin name bit i/o active pull up/down pin function 16 stclk bit stream transfer clock 1 i - p ullup bit stream transfer clock input pin. t he clock is for stream reading in transfer clock sync mode. 205 streq bit stream transfer request 1 i h - bit stream transfer request input pin. when transferring streams in transfer clock sync mode, connect t o vdde. 3 sten bit stream output enable 1 o h - bit stream output enable output pin. 4 to 7,10 to 13 stdata7:0 bit stream data7:0 8 o - - bit stream output port (8bit) pin. t he error code is output in case of an error. 2 tspssync ts/ps sync 1 o h - t his output pin indicates the leading data of the ts/ps packet. 1cycle is set to 'h" at the sync byte of the packet in the case of ts and at the leading byte of the pack header or ps end code in the case of ps.
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 16 2.3.8 test signals table 2.3.8 : test pins pin no. pin symbol pin name bit i/o active pull up/down pin function 201 vpdx - 1 i h - a test pin. for typical usage, connect to vss. 202 testmode - 1 i h pull down a test pin. for typical usage, connect to open or vss . 206 xtst - 1 i l pul l up a test pin. for typical usage, connect to open or vdde .
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 17 3 functional description 3.1 host /sdram interface the host/sdram interface arbitrates bus privilege between the external master connected to this interface and MB86391 internal resources and also controls access to external resources (such as sdram, boot rom, and mpeg decoder). fig. 3.1 shows an example host/sdram interface connection. the next and subsequent chapters show timing diagrams for various accesses. fig. 3.1: host/sdram interfac e connection (example) note: in the case of a 16 mbit sdram , connect adrs13:2 to ba, a10:0 . in the case of a 64mbit sdram , connect adrs13:2 to ba1, a10:0 . keep ba0 fixed to ? h ? or ? l .? install the MB86391 and the sdram as physically close as possible. pul l up the spsdclk signal line with a resistance of 200 w in the vicinity of the sdram . the sp sdclk signal line must be in a pattern of a single stroke, from the MB86391 , the sending end, through the sdram clk to the point of connection to the pull - up resist ance. other signal lines do not require any particular handling such as pull - up. however, take care to avoid unnecessary routing when designing patterns . MB86391 can connect each bit width of boot rom such as 8bit, 16bit and 32bit. (recommended 16bit) recommended boot rom size is over 4mbit. fig. 3.1 : host/sdram interface connection (example) oe dir a b adrs27:26,17:2(i/o) d31:0( i /o) xbgrnt(o) busdir(o) xbusen(o) xcs5,4,0(o) xbreq(i) xbmreq(i) xready(i/o) xrdwr(i/o) xas(i/o) bclk(o)[27mhz] fixed to "l" xspwe(o) spsdclk(o)[54mhz] xspras(o) xspcas(o) sdram 16mbit 2 ( 16bit type) or 64mbit 1 ( 32bit type) mpeg decoder boot rom MB86391 external master bus transceiver (equivalent to lv x245) xcs0 xcs4 or 5 cs oe oe dir a b xcs, dqm a18:16 a15:0 d stdata2:0(o)
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 18 3.1.1 access by external master shown below are diagrams of timing according to which the external master accesses MB86391 internal resources and sdram and peripheral chips (mpeg2 decoder lsi, for example) connected to this interface. 3.1.1.1 MB86391 internal resource accessing (a) write fig. 3.1.1.1 a:MB86391 internal resource access timing (write) (1) the external master asserts xbreq an d requests for bus privilege. (2) before granting bus privilege, the MB86391 sets xas , xrdwr , adrs27:26 , 17:2 and d31:0 to hi - z and busdir to ' l ' ( write direction) and asserts xbgrnt and xbusen to grant bus privilege to the external master. (3) the extern al master outputs valid data to xrdwr, adrs27:26 , 17:2 and d31:0 and asserts the xas signal. note that xbreq must be asserted up to this cycle. (4) the MB86391 fetches the address and control signal statuses in (3) and then negates xbgrnt . at negation of xbgrnt , the external master needs to set xas , xrdwr and adrs27:26 , 17:2 to hi - z . (5) after writing data, the MB86391 asserts xready and notifies the external master of write completion. (6) the MB86391 negates xbusen , sets busdir to 'h' (read direction), and resets to normal state. note: after negating xready, the next request for bus privilege ( asserting xbreq) is allowed. bclk(o) xbreq( i ) xbmreq(i) xbgrnt(o) xas( i /o) xrdwr( i /o) adrs27 :26, 17:2 ( i /o) d31 :0( i /o) xready( i /o) xbusen(o) busdir(o) xcs5 ,4,0(o) all ? h ? all ? h ? all ? h ? all ? h ?
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 19 (b) read fig. 3.1.1.1 b: MB86391 internal resource access timing (read) ) (1) the external master asserts xbreq and requests for bus privilege. (2) before granting bus privilege, the MB86391 sets xas , xrdwr , adrs27:26 , 17:2 and d31:0 to hi - z and busdir to ' l ' (write direction) and then asserts xbgrnt and xbusen to grant bus privilege to the external master. (3) the external master outputs valid data to xrdwr and adrs27:26 , 17:2 and asserts the xas signal. note that xbreq must be asserted up to this cycle. (4) the MB86391 fetches the address and control signal statuses in (3) and then negates xbgrnt . at negation of xbgrnt , the external master needs to set xas , xrdwr and adrs27:26 , 17:2 to hi - z . (5) the MB86391 sets busdir to ? h ? ( read direction ) to allow read data output. (6) the MB86391 outputs valid data to d31:0 at the same time as it asserts xready ( the external m aster fetches read data at this timing ) . (7) the MB86391 negates xbusen and resets to its normal state. note: after negating xready, the next request for bus privilege ( asserting xbreq) is allowed. bclk(o) xbreq( i ) xbmreq(i) xbgrnt(o) xas( i /o) xrdwr( i /o) adrs27 :26, 17:2 ( i /o) d31 :0( i /o) xready( i /o) xbusen(o) busdir(o) xcs5 ,4,0(o) all ? h ? all ? h ? all ? h ? all ? h ?
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 20 3.1.1.2 sdram accessing (a) single write fig. 3.1.1.2 a:sdram access timing (single write) (1) the external master asserts xbreq and requests for bus privilege. (2) before granting bus privilege, the MB86391 sets xas , xrdwr , adrs27:26 , 17:2 and d31:0 to hi - z and busdir to ' l ' (write direction) and then asserts xbgrnt and xbusen to grant bus privilege to the external master. (3) the external master outputs valid data to xrdwr , adrs27:26 , 17:2 , and d31:0 and asserts the xas signal. note that xbreq must be asserted up to this cycle. (4) the MB86391 f etches the address and control signal statuses in (3) and then negates xbgrnt . at negation of xbgrnt , the external master needs to set xas , xrdwr and adrs27:26 , 17:2 to hi - z . (5) the MB86391 re - outputs the address fetched in (4) to the sdram at the command . (6) the MB86391 asserts the xready signal during the cycle to write data to the sdram and notifies it to the external master. (7) the MB86391 negates xbusen , sets busdir to 'h' (read direction), and resets to normal state. note: after negating xready, the next request for bus privilege (asserting xbreq) is allowed. bclk(o) xbreq( i ) xbmreq(i) xbgrnt(o) xas( i /o) xrdwr( i /o) adrs27 :26, 17:2 ( i /o) d31 :0( i /o) xready( i /o) xbusen(o) busdir(o) xcs5 ,4,0(o) all ? h ? all ? h ? all ? h ? all ? h ? ra ca all ? h ?
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 21 (b) single read fig. 3.1.1.2 b: sdram access timing (single read) (1) the external master asserts xbreq and requests for bus privilege. (2) before granting bus privileg e, the MB86391 sets xas, xrdwr, adrs27:26,17:2 and d31:0 to hi - z and busdir to ' l ' (write direction) and then asserts xbgrnt and xbusen to grant bus privilege to the external master. (3) the external master outputs valid data to xrdwr and adrs27:26 , 17:2 a nd asserts the xas signal. note that xbreq must be asserted up to this cycle. (4) the MB86391 fetches the address and control signal statuses in (3) and then negates xbgrnt . at negation of xbgrnt , the external master needs to set xas , xrdwr and adrs27:2 6 , 17:2 to hi - z . (5) the MB86391 re - outputs the address fetched in (4) to the sdram at the command. (6) the MB86391 sets busdir to ? h ? ( read direction ) to allow read data output. (7) the MB86391 asserts the xready signal during the sdram data read cycle and notifies it to the external master. (8) the MB86391 negates xbusen and resets to its normal state. note: after negating xready, the next request for bus privilege (asserting xbreq) is allowed. bclk(o) xbreq( i ) xbmreq(i) xbgrnt(o) xas( i /o) xrdwr( i /o) adrs27 :26, 17:2 ( i /o) d31 :0( i /o) xready( i /o) xbusen(o) busdir(o) xcs5 ,4,0(o) all ? h ? all ? h ? all ? h ? all ? h ? ra ca all ? h ?
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 22 (c) burst write fig. 3.1.1.2 c: sdram access timing (burst write) ) (1) the external master asserts xbreq and requests for bus privilege. (2) before granting bus privilege, the MB86391 sets xas, xrdwr, adrs27:26,17:2 and d31:0 to hi - z and busdir to ' l ' (write direction) and then asserts xbgrnt and xbusen to grant bus privilege to the external master. (3) the external master outputs valid data to xbmreq , xrdwr , adrs27:26 , 17:2 , and d31:0 and asserts the xas signal. note that xbreq must be asserted up to this cycle. (4) the MB86391 fetches the address and control signal statuses in (3) and then negates xbgrnt . at negation of xbgrnt , the external master needs to set xas , xrdwr and adrs27:26 , 17:2 to hi - z . (5) the MB86391 re - outputs the address fetched in (4) to the sdram at the command. (6) the MB86391 asserts the xready signal during the cycle to write data to the sdram and notifies it to the external master. (7) the MB86391 negates xbusen , sets busdir to 'h' (read direction), and resets to normal state. notes: the burst length is fixed to 4. after negating xready, the next request for bus privilege (asserting xbreq) is allowed. burst access extending over 1 kb is not allowed. bclk(o) xbreq( i ) xbmreq(i) xbgrnt(o) xas( i /o) xrdwr( i /o) adrs27 :26, 17:2 ( i /o) d31 :0( i /o) xready( i /o) xbusen(o) busdir(o) xcs5 ,4,0(o) all ? h ? all ? h ? all ? h ? all ? h ? ra ca ca+1 ca+2 ca+3 wd wd+1 wd+2 wd+3 all ? h ?
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 23 (d) burst read fig. 3.1.1.2 d: sdram access timing (burst read) (1) the external master asserts xbreq and requests for bus privilege. (2) before granting bus privilege, the MB86391 sets xas, xrdwr, adrs27:26,17:2 and d31:0 to hi - z and busdir to ' l ' ( write direction and then asserts xbgrnt and xbusen to grant bus privilege to the external master. (3) the external master outputs valid data to xbmreq , xrdwr and adrs27:26 , 17:2 and asserts the xas signal. note that xbreq must be asserted up to this cycle. (4) the MB86391 fetches the address and control signal statuses in (3) and then negates xbgrnt . at negation of xbgrnt , the external master needs to set xas , xrdwr and adrs27:26 , 17:2 to hi - z . (5) the MB86391 re - outputs the address fetched in (4) to the sdram at the command. (6) the MB86391 sets busdir to ? h ? ( read direction ) to allow sdram read data o utput. (7) the MB86391 asserts the xready signal during the sdram data read cycle and notifies it to the external master. (8) the MB86391 negates xbusen and resets to its normal state. notes: the burst length is fixed to 4. after negating xready, the next request for bus privilege (asserting xbreq) is allowed. burst access extending over 1 kb is not allowed. bclk(o) xbreq( i ) xbmreq(i) xbgrnt(o) xas( i /o) xrdwr( i /o) adrs27 :26, 17:2 ( i /o) d31 :0( i /o) xready( i /o) xbusen(o) busdir(o) xcs5 ,4,0(o) all ? h ? all ? h ? all ? h ? all ? h ? ra ca ca+1 ca+2 ca+3 wd wd+1 wd+2 wd+3 all ? h ?
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 24 3.1.1.3 external resource accessing (a) write fig. 3.1.1.3 a: external resource access timing (write) (1) the external master asserts xbr eq and requests for bus privilege. (2) before granting bus privilege, the MB86391 sets xas, xrdwr, adrs27:26,17:2 and d31:0 to hi - z and busdir to ' l ' ( write direction) and then asserts xbgrnt and xbusen to grant bus privilege to the external master. (3) th e external master outputs valid data to xrdwr , adrs27:26 , 17:2 , and d31:0 and asserts the xas signal. note that xbreq must be asserted up to this cycle. (4) the MB86391 fetches the address and control signal statuses in (3) and then negates xbgrnt . at ne gation of xbgrnt , the external master needs to set xas , xrdwr and adrs27:26 , 17:2 to hi - z . (5) after setting xready to hi - z , the MB86391 asserts the appropriate xcsn(n = 5,4) and re - outputs xas , xrdwr , and adrs27:26 , 17:2 fetched in (4) to the external re source. (6) the external resource asserts the xready signal and notifies that data write is complete. (7) the MB86391 negates xbusen and xready , sets busdir to ? h ? ( read direction ) and resets to its normal state. note s : after negating xready, the next r equest for bus privilege (asserting xbreq) is allowed. the external resource needs to be set to hi - z after setting xready to ' h. ' bclk(o) xbreq( i ) xbmreq(i) xbgrnt(o) xas( i /o) xrdwr( i /o) adrs27 :26, 17:2 ( i /o) d31 :0( i /o) xready( i /o) xbusen(o) busdir(o) xcs5 ,4(o) all ? h ? all ? h ? all ? h ? all ? h ? all ? h ? wa wa wa wd wd
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 25 (b) read fig. 3.1.1.3 b: external resource access timing (read) (1) the external master asserts xbreq and requests for bus privilege. (2) before granting bus privilege, the MB86391 sets xas, xrdwr, adrs27:26, 17:2 and d31:0 to hi - z and busdir to ' l ' ( write direction) and then asserts xbgrnt and xbusen to grant bus privilege to the external master. (3) the ext ernal master outputs valid data to xrdwr and adrs27: 26 , 17:2 at the same as it asserts the xas signal. note that xbreq must be asserted up to this cycle. (4) after fetching the address and control signal statuses in (3) , the MB86391 negates xbgrnt . at n egation of xbgrnt , the external master needs to set xas , xrdwr and adrs27:26 , 17:2 to hi - z . (5) after setting xready to hi - z , the MB86391 asserts the appropriate xcsn(n = 5,4) and re - outputs xas , xrdwr , and adrs27:26,17:2 fetched in (4) to the external re source. (6) the external resource asserts the xready signal and notifies that valid data is output to d31:0 . (7) the MB86391 negates xbusen and xready , sets busdir to 'h' (read direction), and resets to normal state. note s : after negating xready, the next request for bus privilege (asserting xbreq) is allowed. the external resource needs to be set to hi - z after setting xready to ' h. " bclk(o) xbreq( i ) xbmreq(i) xbgrnt(o) xas( i /o) xrdwr( i /o) adrs27 :26, 17:2 ( i /o) d31 :0( i /o) xready( i /o) xbusen(o) busdir(o) xcs5 ,4(o) all ? h ? all ? h ? all ? h ? all ? h ? all ? h ? ra ra ra rd
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 26 3.1.2 internal controller master accessing shown below are diagrams of timing according to which the MB86391 internal controller accesses peripheral chips (such as the mpeg2 decoder lsi ) connected to this interface. 3.1.2.1 external resource accessing (a) write fig. 3.1.2.1 a: external resource access timing (write) (1) the MB86391 sets xready to hi - z and asserts xbusen to prepare for accessing. (2) with xcsn (n = 5,4) asserted, the controller selects an external resource and, in conjunction with xas assertion, outputs valid data to xrdwr , adrs27:26 , 17:2 and d31:0 . (3) when the external resource asserts the xready signa l, the MB86391 negates xcsn (n = 5,4) and sets xrdwr to ? h ? ( read, normal state) at the same time as the selection is cancelled (4) the controller negates the xbusen and xready signals to reset to its normal state. note: the external resource needs to be set to hi - z after setting xready to ' h. ' bclk(o) xbreq( i ) xbmreq(i) xbgrnt(o) xrdwr( i /o) xas( i /o) adrs27 :26, 17:2 ( i /o) d31 :0( i /o) xready( i /o) xbusen(o) busdir(o) xcs5 ,4(o) all ? h ? all ? h ? all ? h ? all ? h ? wd wd wa wa
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 27 (b) read fig. 3.1.2.1 b: external resource access timing ( read) (1) the MB86391 sets busdir to ' l ' (read direction ) and xready to hi - z and asserts xbusen to prepare for accessing . (2) with xcsn (n = 5,4) asserted, t he MB86391 selects an external resource and, in conjunction with xas , outputs valid data to adrs27:26 , 17:2 . (3) when the external resource outputs valid data to d31: 0 and asserts the xready signal in the next cycle, the MB86391 read s the data, negates xcsn(n = 5,4) , and cancels the selection. (4) the controller sets busdir to ? h ? ( write direction ) , negates the xbusen and xready signals, and resets to its normal state. note: the external resource needs to be set to hi - z after setting xready to ' h. ' bclk(o) xbreq( i ) xbmreq(i) xbgrnt(o) xrdwr( i /o) xas( i /o) adrs27 :26, 17:2 ( i /o) d31 :0( i /o) xready( i /o) xbusen(o) busdir(o) xcs5 ,4(o) all ? h ? all ? h ? all ? h ? all ? h ? rd ra ra
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 28 3.1.2.2 external boot rom read fig. 3.1.2.2 : external boot rom access timing (read) (1) with xcs0 asserted, t he MB86391 selects the external boot rom, sets busdir to ' l ' (read direction ) and xready to hi - z , and asserts xbusen to prepare for accessing . (2) in conjunction with xas , t he MB86391 outputs valid data to adrs27:26 , 17:2 ( let the external boot rom output read data to the data bus after confirming xcs0) . (3) after proper wait cycles, the MB86391 reads data and negates x cso to cancel the selection. (4) the MB86391 sets busdir to ? h ? ( write direction ) , negates the xbusen and xready signals, and resets to its normal state. note: the number of read wait cycles can be set in the boot program according to the rom in use. wh en defaulted, accessing is done with 30 wait cycles. bclk(o) xbreq( i ) xbmreq(i) xbgrnt(o) xrdwr( i /o) xas( i /o) adrs27 :26, 17:2 ( i /o) d31 :0( i /o) xready( i /o) xbusen(o) busdir(o) xcs0(o) all ? h ? all ? h ? all ? h ? all ? h ? rd ra ra
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 29 3.1.3 interruption 3.1.3.1 internal controller interrupt input (irq9:8) this is the interrupt input to the internal controller. use this input, for example, to control (using dedicated firmware) the mb86373 (mpeg2 decoder lsi) with the internal controller. when not in use, connect the input to either open or vdde ( fixed to high) . 3.1.3.2 host interrupt output (xextirpt) this is the interrupt output from the internal controller to the external host. the firmware dedicated to the internal controller notifies the external host of the end of command processing, for example. (for more information, see " MB86391 control protocol command specification (parallel i/f)").
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 30 3.1.4 address map table 3.1.4 : MB86391 addre ss map address *1 size (byte) cs n description 0x0000000 to 0x0000fff 4k cs0 internal boot rom (for internal boot) 0x0001000 to 0x003ffff 252k cs0 external rom ( for external boot ) 0x4000000 to 0x401ffff 128k cs4 external chip select 4 0x4020000 to 0x403 ffff 128k cs5 external chip select 5 0x8000000 to 0x8 7 fffff 8m - external sdram ( 8 mbytes) *2 0xc000000 to 0xc00ffff 64k - tbc controller & filter 0xc010000 to 0xc01ffff 64k - sdram controller 0xc020000 to 0xc02ffff 64k - dma controller 0xc100000 to 0 xc10ffff 64k - video encoder 0xc200000 to 0xc20ffff 64k - pes converter 0xc300000 to 0xc30ffff 64k - multiplexing controller 0xc400000 to 0xc40ffff 64k - audio buffer 0xc800000 to 0xc80ffff 64k - internal controller (internal register) *1: any space with no description is reserved. *2: an area of 4 mbyte s is actually used.
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 31 3.2 serial interface the serial interface is provided for serial boot and serial api. since this interface does not control flow with hardware, you need to control the flow with fi rmware such as a driver. the firmware dedicated to the internal controller uses ascii mode. 3.2.1 serial interface receive operations the serial interface supports the following receive data formats : mode fm1 fm2 data section bit count (n) description ascii 0 msb 7 ascii code 0x00 to 0x7f and others data32 1 0 32 32 - bit binary data fig. 3.2.1 a - b shows serial interface receive timings . fig. 3.2.1 a: serial interface receive timings (ascii mode) fig.3.2.1b: serial inte rface receiver timing (dara32 mode) there are 2 type transport mode (sclk synchronization mode and start - stop synchronization mode). when using start - stop synchronization mode , pull the sdataout pin down with about 3.3k w . when using sclk synchronization mo de, pull the sdataout pin up with about 3.3k w . it is not possible to change the transport mode during working. in sclk synchronization mode, data is taken on raising edge of sclk. in start - stop synchronizatio n mode, data is taken according to 9600bps with reference to the startbit falling edge of the sdatain signal regardless of sclk. use even parity from fm 1 through datan. after the parity bit, 1 is needed as stopbit. however, if 0 is received at this poin t, it is recognized as a break signal and invalidates receive data. sclk sdatain fm 1=0 fm 2= bit5 bit4 bit3 bit2 bit1 bit0 parity start bit format stop bit bit6 sclk sdatain fm 1=1 fm 2=0 bit31 bit30 bit29 bit28 bit27 bit0 parity start bit format stop bit
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 32 3.2.2 serial interface send operations the serial interface supports the following send data formats mode fm1 fm2 data section bit count (n) description ascii 0 msb 7 ascii code 0x00 to 0x 7f and others data32 1 0 32 32 - bit binary data (for others) fig. 3.2.2 a - b shows serial interface send timings . fig. 3.2.2 a: serial interface send timings (ascii mode) fig. 3.2.2 b: serial interfa ce send timings (data32 mode) there are 2 type transport mode (sclk synchronization mode and start - stop synchronization mode). when using start - stop synchronization mode , pull the sdataout pin down with about 3.3k w . when using sclk synchronization mode, p ull the sdataout pin up with about 3.3k w . it is not possible to change the transport mode during working. use even parity from fm 1 through datan. sclk sdata out fm 1=0 fm 2= bit5 bit4 bit3 bit2 bit1 bit0 parity start bit format stop bit bit6 sclk sdata out fm 1=1 fm 2=0 bit31 bit30 bit29 bit28 bit27 bit0 parity start bit format stop bit
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 33 3.3 sdram interface for video encoding the sdram interface for video encoding controls access to an external sdra m that the video encoder built into this lsi uses to encode video input data. connect either two 16mbit (512k 16bit 2bank configuration ) sdram s or one 64mbit ( 512k 32bit 4bank configuration) sdram . fig. 3.3 shows an example 64mbit sdr am connection. note: install the MB86391 and the sdram as physically close as possible. pull up the sdclk signal line with a resistance of 200 w in the vicinity of the sdram . the sdclk signal line must be in a pattern of a single stroke, from the MB86391 , the sending end, through the sdram clk to the point of connection to the pull - up resistance. other signal lines do not require any particular handling such as pull - up. however, take care to avoid unnecessary routing when designing patterns. fig. 3.3 : example video encoding sdram interface connection sdadrs11:0 sddata31:0 sddqm xsdwe xsdcas xsdras MB86391 ba1, a10:0 dq31:0 dqm3:0 we cas ras 64mbit sdram ( mb81f643242b and others ) video encoding sdram interface sdclk xsdcs sdcke cs cke clk ba0 ?fixed to h ? or ? l ?
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 34 3.4 video input interface the video input interface is a dedicated interface between the MB86391 and an external device (such a an ntsc decoder) connected to the MB86391 . fig. 3.4 shows an example connection. fig. 3.4 : example video input interface connection dvideo7:0 vclk xvsync xhsync field xvalid MB86391 vdo7:0 lcc rts0 rts1 ntsc decoder (saa7113) video input interface ? h ? ? h ?
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 35 3.4.1 input formats the video input interface is compatible with the following data input formats : (a) d1 parallel input mode input d1 format data t o the dvideo7:0 pin. the xvsync , xhsync , field and xvalid pins are not used ( keep them fixed to h .) since synchronization information is extracted from the sav/eav signal in the d1 data. (b) y/c multiplex input mode input video data multiplexed in 4:2:2 format (cbycr in that order ) to dvideo7:0 pin as well as sync and valid pixel signals to the xvsync , xhsync , field and xvalid pins.
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 36 3.5 audio input interface the audio input interface is a dedicated audio data interface between the MB86391 and the audio a/d conve rter connected to the MB86391 . fig. 3.5 shows an example connection. note : mclki must be in sync with asclk . fig. 3.5 : example audio input interface connection (master mode) note : mclki must be in sync with asclk . fig. 3.5 : example audio input interface connection (slave mode) asclk alrck aclk adata mclki MB86391 256fs audio adc pll 27mhz oscillation audio input interface lr_clock bit_clock data asclk alrck aclk adata mclki MB86391 256fs audio adc pll 27mhz oscillation audio input interface lr_clock bit_clock data
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 37 3.5.1 master/slave mode master (the MB86391 outputs aclk and alrck ) and slave (input of aclk and alrck from the audio a/d converter to the MB86391 ) modes can be switched. 3.5.2 input formats setting each of the following parameters allows compatibility with various input formats : (1) msb first / lsb first of data (2) packing alrck with data (left/right packing) ) (3) alrck polarity ( ? h ? =lch, ? l ? =rch / ? l ? =lch ? h ? =rch) (4) phase relationsh ip between alrck and data (compatible with i 2 s interface ) the phase relationship between alrck and aclk is adjustable by 256 fs in master mode. fig. 3.5.2 : input formats aclk(i/o) alrck(i/o) adata(i) d d d d d d d d d d d d d lch rch msb/lsb 16bit lsb/msb msb/lsb 16bit lsb/msb lch rch lch rch lch rch d d d d d d d d d d d d msb/lsb 16bit lsb/msb msb/lsb 16bit lsb/msb d d
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 38 3.6 bit stream output port the bit stream output port is compatible with various transfer modes described next : (a) 27 mhz sync mode this mode is for storage function products. the pcr(scr) is made by the calculated value from bit - stream and datasize. fig. 3.6 a: 27 mhz sync mode timings (1) when ready to receive streams, set streq to 'h.' (2) when valid data exists, the MB86391 sets sten to ? h ? at stdata to instruct data fetching. it also sets the tspssync signal simultaneously to 'h' at the sync byte "0x47" if the stream is ts, and at pack start code " 0x000001ba" or at the leading byte of the program end code "0x000001b9" if the stream is ps. notes: there is an instance during which two pieces of data are output at maximum even if streq is set ' l .' limit the duration during which streq is set to ? l ? whi le encoding to a few tens of clocks. the bit rate must also be maintained on the average (the MB86391 is equipped with an internal buffer to temporarily store bit streams. however, the buffer fails if bit streams are not read for a lengthy period of time .) (b) handshake mode this mode is for storage function products. the pcr(scr) is made by the calculated value from bit - stream and datasize. fig. 3.6 b: handshake mode timings bclk(o) streq( i ) sten(o) valid stdata(o) tspssync(o) valid valid valid bclk(o) streq( i ) sten(o) stdata(o) tspssync(o) valid valid
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 39 (1) when ready to receive streams, set streq to 'h.' (2) whe n valid data exists, the MB86391 changes sten ? h ? ? ? l ? ? ? h ? at stdata . it simultaneously sets the tspssync signal to 'h' at the sync byte "0x47" if the stream is ts, and at the pack start code "0x000001ba" or at the leading byte of the program end code "0x 000001b9" if the stream is ps. note : limit the duration during which streq is set to ? l ? while encoding to a few tens of clocks. the bit rate must also be maintained on the average (the MB86391 is equipped with an internal buffer to temporarily store bit streams. however, the buffer fails if bit streams are not read for a lengthy period of time.) (c) external clock sync mode (cbr) this mode is for real time transfer function products. the pcr(scr) is made by stclk. fig. 3.6 c: external clock mode (cbr) (1) input the transfer clock to stclk according to the bit and set streq to ' h .' (2) while transferring, the MB86391 outputs 'h' to sten at all times and outputs valid data according to the external clock stclk . it also simultaneously s ets the tspssync signal to 'h' at the sync byte "0x47" if the stream is ts, and at the pack start code "0x000001ba" or at the leading byte of the program end code "0x000001b9" if the stream is ps. note: stclk should be input over 1/8 x system bit - rate. ( ex: when the system bit - rate is 8mbps, stclk should be over 1mhz.) when stclk is more high frequency than system bit - rate which is setted, stuffing is implemented. (d) external clock sync mode (vbr) this mode is for real time transfer function products. the pcr(scr) is made bystclk. fig. 3.6 d: external clock mode (vbr) stclk(i) streq( i ) sten(o) valid stdata(o) tspssync(o) valid valid valid stclk(i) streq( i ) sten(o) valid stdata(o) tspssync(o) valid valid valid
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 40 (1) input the transfer clock to stclk according to the bit and set streq to ' h .' (2) while transferring, the MB86391 outputs 'h' to sten at all times and outputs val id data according to the external clock stclk . it also simultaneously sets the tspssync signal to 'h' at the sync byte "0x47" if the stream is ts, and at the pack start code "0x000001ba" or at the leading byte of the program end code "0x000001b9" if the s tream is ps. note: s tuffing is implemented as necessary .
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 41 3.7 error notification function the MB86391 has a built - in function to notify outside of an error when it occurs. in case of an error, it sets the xerror pin to ' l ' to output error information from the bit stream output port. when the error information is output, the sten and tspssync pins are set to 'l' (fig. 3.7 ) . table s 3.7 a and 3.7 b list the pins and error descriptions related to occurrence of errors. table 3.7 a: error list pin status stdata xerror 7 6 5 4 3 2 1 0 sten tspssync error description 1 - - - - - - - - - - no error (normal stream output) 0 0 0 1 sub - error code 0 0 timeout error 0 0 1 0 sub - error code 0 0 external illeg al access error 0 1 0 0 sub - error code 0 0 program error table 3.7 b: sub - error code list sub - error code description 0 0 0 0 0 reset status 0 0 0 0 1 firm ware startup 0 0 0 1 0 to 0 1 1 1 1 reserved 1 0 0 0 0 boot complete 1 0 0 0 1 boot in progress 1 0 0 1 0 boot mode error 1 0 0 1 1 boot header keyword error 1 0 1 0 0 boot header checksum error 1 0 1 0 1 data block header keyword error 1 0 1 1 0 data block header checksum error 1 0 1 1 1 data block checksum error 1 1 0 0 0 to 1 1 1 1 1 reserved note: being dependent on the firmware, this code is subject to change and addition. fig. 3. 7 : error information output timings bclk(o) tspssync(o) sten(o) error stdata(o) xerror(o) 2cycle(max.)
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 42 3.8 boot operations the MB86391 starts booting operations when the internal controller starts the boot program of the internal rom. the program required for the operation is downloaded to the sdram interface connected to the host/sdram according to the processing flow in fig. 3.8. each downloading procedure is described in the next and subsequent chapters. fig. 3.8 : booting flow check external rom keyword keyword ok? external rom download yes initialize check serial api data exists? serial download yes check parallel api startup request ? immediately s tart sdram. yes no no no start boot
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 43 3.8.1 downloading from the external rom this mode downloads the program from an external rom to the sdram. when the boot program of the internal rom confirms of the external rom, start d ownloading from the external rom to sdram via MB86391. after downloading , MB86391 starts the program on sdram. when the existence of an external rom is confirmed, the program re - sets the wait count specified with "wait" in the header to download the data to be downloaded. the download data configuration is not dependent on the rom bus width. 3.8.2 serial download the internal rom boot program of the MB86391 sets to either serial api or sdram direct download mode (see chapter 3.8.3) if it confirms that there i s no external rom. upon arrival of an interrupt from the serial interface, the internal rom boot program of the MB86391 receives the data transferred with the serial interface and, if the header of this data is configured as shown in table 3.8.2a, download s it as serial api. the internal serial interface of the MB86391 supports data32 and ascii send and receive data formats (see chapter 3.2). since data can also be sent with sclk synchronization or asynchronization (9,600bps), four types of serial booting are available (data32/sclk synchronization, ascii/sclk synchronization, data32/asynchonization, and ascii/asynchronization). 3.8.3 direct sdram downloading the sdram connected to the MB86391 host/sdram is assigned in the cs1 space by the internal rom boot initi alization routine. from the host interface with the parallel api, the entire sdram area is accessible if used with a bank register. this enables to write the program and data (including the header in table 3.8.3) from the host/sdram interface to the sdra m by directly accessing the memory. during this period, the internal rom boot program of the MB86391 is in an infinite loop waiting for interruption. therefore, from the host/sdram interface, instruct to start the program by executing parallel api interr uption (by writing to the register) after direct downloading to the sdram is complete. the internal rom boot program of the MB86391 verifies that the appropriate header is in from the sdram leading address and then jumps to the entry address to start execu ting the program.
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 44 4 electrical characteristics 4.1 maximum ratings table 4.1 : maximum ratings item symbol max. ratings unit vddi - 0.5 to 2.5 vdd e - 0. 5 to 4.0 supply voltage *1 a vdd - 0.5 to 2.5 v input voltage vi - 0.5 to vdde+0.5 ( 4.0) v output voltage vo - 0.5 to vdde+0.5 ( 4.0) v output current io + 13/ - 13 ma operating temperature ta - 20 to 85 c storage temperature tst - 55 to 125 c *1: vddi ? internal logic power supply, vdde ? external i/o power supply, avdd - pll power supp ly
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 45 4.2 recommended operating conditions 4.2.1 recommended operating conditions table 4.2.1 : recommended operating conditions ratings item symbol min. typical max. unit vddi 1.65 1.8 1.95 vdd e 3.0 3.3 3.6 supply voltage a vdd 1.65 1. 8 1.95 v h - level input voltage 3.3v vih 2 .0 - vdde+0.3 v l - level input voltage 3.3v vil - 0.3 - 0.8 v operating temperature ta - 20 25 85 c 4.2.2 precautions when connecting the power although vddi , vdde and avdd can be turned on an d off in any order, fujits u recommends the following order: turning on :vddi , avdd( internal ) ? vdde (external) ? signals turning off :signals ? vdde (external) ? vddi , avdd (internal) do not keep vdde (external) alone pressed (for more than a few seconds) with vddi and avdd (internal) disconnected. the following power supply sequence applies to 5v tolerant i/o before turning on the device, never input 5v input signals (observe the maximum ratings at all times). otherwise, you might destroy the device. after turning on the power, keep the pllthr pin set to the l level for more than 2 m s . next, set the pllthr pin to the h level and then input the l level to the xreset signal for more than 300 m s .
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 46 4.3 dc characteristics measurement conditions :vddi=1.65 to 1.95v , vdde=3.0 to 3.6 , vss=0.0v , ta= - 20 to 85 c ratings item symbol min. typical max. unit h - level output voltage *1 voh vdde - 0.2 - vdde v l - level output voltage *2 vol 0.0 - 0.2 v h - level output current *3 ioh1 *6 ioh2 *5 - 4. 0 - 8. 0 - - ma l - level output current *4 iol1 *6 iol2 *5 4. 0 8. 0 - - ma input leakage current il - - + 5 / - 5 m a p ull up/down resistance rp 10 25 70 k w pin capacity c - - 16 pf *1: condition ioh= - 100 m a *2: condition iol=100 m a *3: condition voh=vdde - 0.4v *4: condition vol=0.4v *5: bclk, spsdclk, and sdclk signal output characteristics *6: output characteristics of signals other than those in *5
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 47 4.4 ac characteristics 4.4.1 overall control 4.4.1.1 clock input standard item symbol condition min. typical max. unit mclki frequency f mclki - 27 - mhz mclki h duration t hmclk i 14 - - ns mclki l duration t lmclki 14 - - ns mclki 1 / f mclki t lmclki t hmclki
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 48 4.4.1.2 reset input (a) after turning the power on standard item symbol condition min. typical max. unit pllthr l duration t lpllthr 2 - - m s xreset l duration t lreset 300 - - m s (b) other than aft er turning the power on standard item symbol condition min. typical max. unit xreset l duration t lrst 500 - - ns pllthr t lpllthr t lreset xreset t lrst xreset
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 49 4.4.2 host /sdram interface 4.4.2.1 host interface clock (bclk) standard item symbol condition min. typical max. unit bclk frequency f bcl k - 27 - mhz bclk h duration t hbclk 13 - - ns bclk l duration t lbclk 13 - - ns bclk 1 / f bclk t lbclk t hbclk
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 50 input sigals output signals bclk t iadrss , t ids , t irqs , t iass , t irws , t bmrqs , t brqs , t irdys adrs, d, irq, xas, xrdwr, xbmreq, xbreq, xready t iadrsh , t idh , t irqh , t iash , t irwh , t bmrqh , t brqh , t irdyh bclk t oadrsd , t odd , t oasd , t orwd , t csd , t bgrntd , t bed , t bdd , t ordyd , t eid , t errd adrs, d, xas , xrdwr, xcs, xbgrnt, xbusen, busdir, xready, xextirpt, xerror
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 51 standard item symbol condition min. typical max. unit address input setup time t ia d rs s 7 - - ns address input hold time t ia d rs h 0 .5 - - ns address output delay time t oa d rsd 3 - 12 ns data input setup time t i ds 7.5 - - ns data input hold time t i dh 0 - - ns data output delay time t o dd 3 - 12 ns irq setup time t irq s 7 - - ns irq hold time t irq h 0 - - ns xbreq setu p time t brq s 7 - - ns xbreq hold time t brq h 0 - - ns xbmreq setup time t bmrq s 7 - - ns xbmreq hold time t bmrq h 0 - - ns xbgrnt delay time t bgrntd 3 - 12 ns x rdwr input setup time t irw s 7 - - ns x rdwr input hold time t irw h 0 - - ns x rdwr out put delay time t orwd 3 - 12 ns x as input setup time t ia ss 7 - - ns x a s input hold time t ia sh 0 - - ns x a s output delay time t oa s d 3 - 12 ns x cs delay time t cs d 3 - 12 ns x ready input setup time t ir dys 7 - - ns x ready input hold time t ir dyh 0 - - ns x ready output delay time t or dy d 3 - 12 ns xbusen delay time t bed 3 - 12 ns busdir delay time t bd d 3 - 12 ns xextirpt delay time t eid 3 - 12 ns xerror delay time t errd 3 - 12 ns
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 52 4.4.2.2 sdram interface signals clock (spsdclk) standard item symbol condi tion min. typical max. unit spsdclk frequency f spsdclk - 54 - mhz spsdclk h duration t hspsdclk 6.5 - - ns spsdclk l duration t lspsdclk 6.5 - - ns input signals output signals spsdclk 1 / f spsdclk t lspsdclk t hspsdclk spsdclk t rds d31 :0 t rdh spsdclk d31 :0, adrs14:2, xspwe, xspcas, xspras, spcke t wdd , t adrsd , t spwed , t spcasd , t sprasd , t spcked
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 53 standard item symbol condition min. typical max. unit address output delay time t a d rsd 3 - 12 ns read data setup time t r ds 7 - - ns read data hold time t r dh 0 - - ns data output delay time t w dd 3 - 12 ns spwe delay time t spwed 3 - 12 ns spcas delay time t spcasd 3 - 12 ns spras delay time t sprasd 3 - 12 ns spcke delay time t spcked 3 - 12 ns
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 54 4.4.3 serial interface clock (sclk) standard item symbol condition min. typical max. unit sclk frequency f sclk - - 2 mhz sclk h duration t hsclk 200 - - ns sclk l duration t lsclk 200 - - ns input signal s output signals sclk 1 / f sclk t lsclk t hsclk sclk t sdis sdatain t sdih sclk sdataout t sdod
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 55 standard item symbol condition min. typical max. unit serial data input setup time t sdis 100 - - ns serial data input hold time t s d ih 10 0 - - ns serial data output delay time t sdo d - - 160 ns
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 56 4.4.4 sdram inte rface for video encoding clock (sdclk) standard item symbol condition min. typical max. unit sdclk frequency f sdclk - - 54 mhz sdclk h duration t hsdclk 6.5 - - ns sdclk l duration t lsdclk 6.5 - - ns input signal s output signals sdclk 1 / f sdclk t lsdclk t hsdclk sdclk t rsds sddata31 :0 t rsdh sdclk sddata31 :0, sdadrs11:0, sddqm, xsdwe, xsdcas, xsdras, xsdcs, sdcke t wsdd , t sadrsd , t sddqm , t sdwed , t sdcasd , t sdrasd , t sdcsd , t sdcked
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 57 standard item symbol condition min. typical max. unit address output delay time t sa d rsd 3.5 - 13 ns read data setup time t rs ds 5.5 - - ns read data hold time t rs dh 0 - - ns data output delay time t ws dd 3.5 - 13 ns xsddqm delay time t sddqm 3.5 - 13 ns xsdwe delay time t sdwed 3.5 - 13 ns x s d cas delay time t sdcasd 3.5 - 13 ns x s d ras delay time t sdrasd 3.5 - 13 ns x s d c s delay time t sdcsd 3.5 - 13 ns x s d cke delay time t sdcked 3.5 - 13 ns
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 58 4.4.5 video input interface clock (vclk) standard item symbol c ondition min. typical max. unit vclk frequency f vclk 27 - 36 mhz vclk h duration t hvclk 11 - - ns vclk l duration t lvclk 11 - - ns input signal standard item symbol condition min. typical max. unit xvsync setup time t vsync s 10 - - ns xvsync hold time t vsync h 0 - - ns xhsync setup time t hsyncs 10 - - ns xhsync hold time t hsynch 0 - - ns field setup time t flds 10 - - ns field hold time t fldh 0 - - ns xvalid setup time t vlds 10 - - ns xvalid hold time t vldh 0 - - n s dvideo setup time t dvds 10 - - ns dvideo hold time t dvdh 0 - - ns vclk 1 / f vclk t lvclk t hvclk vclk t vsyncs , t hsyncs , t flds , t vlds , t dvds xvsync, xhsync, field, xvalid, dvideo t vsynch , t hsynch , t fldh , t vldh , t dvdh
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 59 4.4.6 audio input interface (a) in master mode system clock input (asclk) standard item symbol condition min. typical max. unit asclk frequency t asclk - 1/256fs - ns asclk h dur ation t hasclk 30 - - ns asclk l duration t lasclk 30 - - ns note : fs: audio sampling frequency audio bit clock output (aclk) standard item symbol condition min. typical max. unit aclk frequency t aclko - 1/64fs - ns aclk h duration t haclko 135 - - ns aclk l duration t laclko 135 - - ns aclk delay time t aclkd 3 - 15 ns note: fs : audio sampling frequency asclk t aclko t laclko t haclko t aclkd aclk asclk t asclk t lasclk t hasclk
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 60 serial audio data input signals audio sampling clock output signals standard item symbol condition min. typical max. unit ad ata setup time t a d s 50 ns adata hold time t a dh 50 ns alrck cycle time t alrcko 20 m s alrck delay time t alrckd 3 15 ns aclk t ads adata t adh asclk alrck t alrckd t alrcko
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 61 (b) in slave mode audio bit clock input (aclk) standard item symbol condition min. typical max. unit aclk cycle d uration t aclki - 1/64fs - ns aclk h duration t hsdclk 135 - - ns aclk l duration t lsdclk 135 - - ns note : fs: audio sampling frequency serial audio data input signals audio sampling clock input signals aclk t aclki t laclki t haclki aclk t ads adata t adh aclk alrck t alrckh t alrcki t alrcks
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 62 standard item symbol condition min. typical max. unit adata setup time t a d s 50 ns adata hold time t a dh 50 ns alrck cycle time t alrcki 20 m s alrck setup time t alrcks 50 ns alrck hold time t alrckh 50 ns
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 63 4.4.7 bit stream output port (a) 27 mhz sync / handshake mode input sing nals output signals standard item symbol condition min. typical max. unit streq setup time t bstrqs 8 ns streq hold time t bstrqh 0 ns sten delay time t bsted 5 15 ns stdata delay time t bstdtd 5 15 ns tspssync delay time t btpsyncd 5 15 ns bclk t bstrqs streq t bstrqh bclk sten, stdata, tspssync t bsted , t bstdtd , t btpsyncd
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 64 (b) transfer clock sync mode clock (stclk) standard item symbol condition min. typical max. unit stclk cycle duration t stclk 150 ns stclk h duration t hstclk 60 ns stclk l duration t lstclk 6 0 ns input signal s output sign als stclk t stclk t lstclk t hstclk stclk t strqs streq t strqh stclk sten, stdata, tspssync t sted , t stdtd , t tpsyncd
fujitsu limited proprietary and confidential MB86391 12, november 2001 product specification rev. 1.1 65 standard item symbol condition min. typical max. unit streq setup time t strqs 0 ns streq hold time t strqh 60 ns sten delay time t sted 103 ns stdata delay time t stdtd 103 ns tspssync delay time t tpsyncd 103 ns

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